SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
CXL: Advancing Coherent Connectivity
Abstract
Delivering high-performance interoperable computational infrastructures is vital to meeting the exponential growth of global data for applications in Artificial Intelligence, Machine Learning, Analytics, Cloudification of the Network and Edge, and High-Performance Computing. CXL™ (Compute Express Link™), an open interconnect standard, delivers coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices to deliver optimized performance in evolving usage models. The CXL Consortium has released CXL specification 3.0, expanding on previous versions to increase scalability and optimize system-level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. In addition to memory pooling, CXL 3.0 enables memory sharing, which allows system designers to utilize machine clusters to address modern issues through memory constructs. The CXL 3.0 specification also introduces fabric capabilities beyond the traditional tree-based architectural structures of PCI Express® (PCIe®) and previous CXL iterations. This panel session will begin with an update from the Consortium, highlighting updates to the CXL specification and the new usage models enabled by CXL. An in-depth discussion from our panelists will explore the importance of delivering interoperable ecosystems, allowing enterprises and system architects to address modern challenges within the supercomputing community. Attendees will have an opportunity to ask the panel of experts questions about advancing their existing architectures and CXL implementations.
Learning Objectives
- Gain insight into the features of the CXL 3.0 specification
- Introduce updates from the Consortium and CXL technology
- Explore the importance of delivering interoperable ecosystems and advancing existing architectures
Related Sessions
SNIA SDXI Specification v1.0 and Beyond
SDXI v1.0 is a standard for a memory-to-memory data mover and acceleration interface that is extensible, forward-compatible, and independent of I/O interconnect technology. Among other features, SDXI standardizes an interface and architecture that can be abstracted or virtualized with a well-defined capability to quiesce, suspend, and resume the architectural state of a per-address-space data mover. This specification was developed by SNIA’s SDXI Technical Working Group, comprising of 89 individuals representing 23 SNIA member companies. As new memory technologies get adopted and memory fabrics expand the use of tiered memory, SDXI Specification v1.0 will be enhanced with new accelerated data movement operations and use cases. This talk gives an overview of the SDXI’s use cases, important features of SDXI specification v1.0, and what features can be expected with new versions of the specification.
CXL Memory Disaggregation and Tiering: Lessons Learned from Storage
The introduction of CXL has significantly advanced the enablement of memory disaggregation. Along with disaggregation has risen the need for reliable and effective ways to transparently tier data in real time between local direct attached CPU memory and CXL pooled memory. While the CXL hardware level elements have advanced in definition, the OS level support, drivers and application APIs that facilitate mass adoption are still very much under development and still in discovery phase. Even though memory tiering presents new challenges, we can learn a great deal from the evolution of storage from direct attached to storage area networks, software defined storage and early disaggregated/composable storage solutions such as NVMe over fabrics. Presented from the viewpoint of a real time block storage tiering architect with products deployed in more than 1 million PCs and servers.
CXL: Advancing Coherent Connectivity
Delivering high-performance interoperable computational infrastructures is vital to meeting the exponential growth of global data for applications in Artificial Intelligence, Machine Learning, Analytics, Cloudification of the Network and Edge, and High-Performance Computing. CXL™ (Compute Express Link™), an open interconnect standard, delivers coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices to deliver optimized performance in evolving usage models. The CXL Consortium has released CXL specification 3.0, expanding on previous versions to increase scalability and optimize system-level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. In addition to memory pooling, CXL 3.0 enables memory sharing, which allows system designers to utilize machine clusters to address modern issues through memory constructs. The CXL 3.0 specification also introduces fabric capabilities beyond the traditional tree-based architectural structures of PCI Express® (PCIe®) and previous CXL iterations. This panel session will begin with an update from the Consortium, highlighting updates to the CXL specification and the new usage models enabled by CXL. An in-depth discussion from our panelists will explore the importance of delivering interoperable ecosystems, allowing enterprises and system architects to address modern challenges within the supercomputing community. Attendees will have an opportunity to ask the panel of experts questions about advancing their existing architectures and CXL implementations.
CXL and the Art of Hierarchical Memories: Their Management and Use
New technologies and platforms have laid waste to the assumptions of fixed-size, monolithic memory. Multiple layers of CXL-attached memory and persistent memory now provide a wide variety of types and speeds of memory available to developers of future systems. We will compare these various tiers of memories, whether inside the box or remotely attached. Next, we will examine how users and consumers of multi-tiered memory can make use of their varying characteristics, such as latency and persistence. We'll discuss the idea of application-specific memory, as well as some of the libraries available for tiering. We'll touch on the various different schemes for how to use the multiple layers of memory. Finally, we'll discuss the ways to manage the hierarchies and optimize access to them by modeling the ways applications can use them. This helps make the most of the hierarchy.
Fabric Attached Memory – Hardware and Software Architecture
HPC architectures increasingly handle workloads where the working data set cannot be easily partitioned or is too large to fit into node local memory. We have defined a system architecture and a software stack to enable large data sets to be held in fabric-attached memory (FAM) that is accessible to all compute nodes across a Slingshot-connected HPC cluster, thus providing a new approach to handling large data sets. Emerging AI and data analytics workloads are increasingly becoming important for HPC architectures because HPC clusters provide computation capabilities needed at scale; however a divide still exists between traditional HPC, AI, and data analytics applications, because the three communities use very different programming models. The architecture leverages emerging hardware capabilities such as CXL along with ideas from both HPC and high performance data analytics software to support AI and data analytics on HPC clusters. This presentation will cover the architecture, the software stack and its value using a use case: an Arkouda-based proxy application for real-time data analytics.
Compute Express Link™ (CXL™): Enabling an interoperable ecosystem for heterogeneous memory and computing solutions
CXL, an open industry standard interconnect, addresses the growing high-performance computational workloads to support heterogeneous processing and memory systems with applications in Artificial Intelligence, Machine Learning, Analytics, Cloud Infrastructure, Cloudification of the Network and Edge, communication systems, and High-Performance Computing by enabling coherency and memory semantics on top of PCI Express® (PCIe®) based I/O semantics to optimize performance in evolving usage models. The CXL Consortium released the CXL 3.0 specification in August 2022 to increase scalability and optimize system level flows with expanded fabric capabilities and management, improved memory sharing and pooling, enhanced coherency, and peer-to-peer communication. This presentation will provide insights into new features of the CXL 3.0 specification and introduce updates in the specification.
