Explore the Compute Express Link™ (CXL™) Device Ecosystem and Usage Models - A Panel
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Company : Astera Labs
Delivering high-performance interoperable computational infrastructures is vital to meeting the exponential growth of global data for applications in Artificial Intelligence, Machine Learning, Analytics, Cloudification of the Network and Edge, and High-Performance Computing. CXL™ (Compute Express Link™), an open interconnect standard, delivers coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices to deliver optimized performance in evolving usage models.
The CXL 3.1 specification introduces CXL fabric manager and extensions, Trusted-Execution-Environment Security Protocol (TSP), and facilitate memory sharing between accelerators and GPUs. This panel presentation will introduce the new features and explore how CXL attached memory to meet the increased memory capacity and bandwidth for HPC, AI, and ML applications in modern data centers. Expert representatives from CXL Consortium member companies will highlight ROI examples when implementing CXL attached memory.