Robert Blankenship

The CXL interface adds both a memory and a caching protocol between a host CPU and a device. The Memory Protocol enables a device to expose memory region to the host to be used as system memory. The Caching Protocol can be used to directly cache host memory allowing devices to implement advanced flows like data prefetching and hardware atomics within a cache. Devices supporting both protocols can directly access the memory exposed to the host enabling high performance accelerator and computation storage use cases that are tightly coupled with the host CPU.