SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
New memories like MRAM, ReRAM, PCM, and FRAM are vying to replace embedded flash and, eventually, even embedded SRAM. In our Deep Look at New Memories webinar, our speakers Arthur Sainio, SNIA Persistent Memory Special Interest Group Co-Chair, Tom Coughlin of Coughlin Associates, and Jim Handy of Objective Analysis took a present and future look, explaining the applications that have already adopted new memory technologies in the marketplace, their impact on computer architectures and AI, the outlook for important near-term changes, and how economics dictate success or failure. If you have not yet watched the webinar, check it out in our SNIA Educational Library!
The audience was highly engaged and asked many interesting questions, some which were answered at the end of the webinar. However, we could not get to all of them, so our Q&A covers those that remained. Feel free to reach out to us at askcms@snia.org if you have more!
Q: How long will it take for a new memory to replace DRAM?
A: DRAM has a couple of things going for it that any prospective rival does not, and that’s the fact that it’s already produced in enormous volumes (about 20 billion chips per year) and it has more than five decades of learning behind it. Any rival will need to compete against DRAM on cost, and that will naturally take advantage of the new memory’s ability to go far beyond DRAM’s scaling limit, but the new memory will also need to be produced in high enough volume to supersede DRAM’s advantages in volume and learning. That’s going to take some time, but we think that the mid-2030s may see a transition underway.
Q: You talked a lot about MRAM applications, how are other new memories being used?
A. Our focus on MRAM is largely because of its widespread use right now. ReRAM is just beginning to find more applications and is a big focus of leading foundries. Panasonic introduced a ReRAM-based MCU way back in 2012, but they have been pretty alone. Another company that’s pretty alone STMicroelectronics, who ships the world’s only PCM-based MCU. Back when Intel was pursuing Optane we focused a lot of attention on PCM because Optane used PCM and ran in pretty high volume. From a unit-volume standpoint, though, FRAM beats all others in an extremely narrow application space: RFID fare cards for trains. These chips are really tiny, though, so they don’t consume many wafers.
Q. Will any of these memories move from back end of line to front end of line production and why or why not?
A. There’s a big advantage in being back end of line (BEOL) that has been used to reduce the cost of 3D NAND. With BEOL you can build the memory bits on top of the support logic to make a significantly smaller chip. Today companies are just starting to migrate from that to a hybrid-bonded approach, where two wafers on two different process lines are used, one to make the bits and one to make the logic. A BEOL-friendly bit cell lends itself to this approach too.
Q. What role could these new non-volatile memories play in chiplet technology/heterogeneous integration?
A. Future processors will have a logic chip for the processor and supporting chiplets for memory, whether it’s firmware memory, scratchpad memory, or a cache. These new technologies can support all three, although most of today’s research is focused on slower versions that won’t be too useful for the lowest-level caches closest to the processor. Over time we expect that to change, too.
Q. What role will these memories play in CXL-based memory systems?
A. CXL provides a wide variety of solutions to computing architecture. It supports memories of all kinds: Fast & slow, volatile & nonvolatile, byte write and block erase. Both CXL and NVMe can support any of these memory types, but NVMe is not fast enough to take advantage of really fast memories, so CXL is likely to be used in systems that need NVMe-like support at speed significantly faster than NVMe.
Q. How important is radiation resistance in memory?
A. That’s a tough question, because radiation barely makes a difference to a PC or smart phone user, but it’s a “Make or Break” issue for aerospace and certain other applications. There’s radiation everywhere, and it corrupts bits. Sometimes that just means that your PC bombs, resulting in “vocabulary enrichment” as you reboot. If a program bit is lost in a deep-space satellite, it’s likely that the entire billion-dollar mission will become a total loss. Also, there’s a lot of radiation in space, but the earth’s atmosphere absorbs a lot it before it gets down to the surface, so it’s less of an issue down here than it is in space.
Radiation can have a significant impact on DRAM memory used in networking equipment. It can cause bit flips referred to as Single Event Upsets (SEUs) which requires network equipment to be restarted. Using memory that has more resistance to radiation is beneficial in this case. If you are interested in this topic, check out a blog post from Jim Handy on memory issues in space medical applications.
Q. How much are these various new memories affected by electromagnetic fields?
A. They’re not as susceptible to stray fields as many people think. While you can’t put an MRAM inside of the powerful magnetic coil of an MRI imager, a lot of other common sources of magnetism are not a concern. Jim Handy’s working with MRAM makers and leading MRAM researchers to put together a table that illustrates where this stands in real-life terms that anyone can understand.
Q. What sort of manufacturing volume will new memory need to replace DRAM, assuming it had similar performance?
A. Based on the NAND flash crossover with DRAM prices in 2004, and upon Intel’s trouble getting Optane costs competitive with DRAM, despite Optane’s significantly smaller die size, Objective Analysis estimates that the wafer volume of a competing technology must come within an order of magnitude of that of DRAM’s for its costs to fall below DRAM’s.
Q. How will AI affect new memory demand, both in the data center and for consumer applications?
A. For anything to play a part in AI or any other computing application, it must provide a compelling cost advantage over more established technologies. In the data center that cost includes energy costs as well as the cost of the computing equipment itself, so if a slightly more costly technology can reduce energy costs so much that the total cost of ownership (TCO) is reduced, then it will find broad acceptance. These technologies aren’t there yet. Portable applications are somewhat different, because these memories can often reduce the cost of the system’s battery, creating a lower TCO than established technologies can do.
Q. You mentioned a 10nm limit for DRAM, are there ways that DRAM might get around that limit--such as with 3D memory?
A. DRAM’s kind of 3D already, so the benefit of turning it on its side as the industry did with NAND flash doesn’t bring DRAM anywhere near the benefits that the 3D switch caused for NAND flash. One very promising approach is to take some of the FRAM materials and use them to shrink the DRAM’s capacitor, but if you do that, you may as well just build an FRAM. Another possibility is to convert to a gain cell, which uses 2-3 transistors to replace the DRAM’s 1-transistor, 1-capacitor cell. One huge advantage of the gain cell is that it can shrink with the process, rather than being limited by the size of the capacitor. It’s early in the game, though, and although we are certain that an ingenious solution will get us past this hurdle, it’s too early to tell what that solution will be.
, though, that shouldn’t be that much of a problem since it’s a transactional protocol. The reads, then, will probably rival DRAM speeds for MRAM and for resistive RAM (MRAM might get up to DRAM speeds with its writes too). In fact, there are technologies like spin-orbit torque and even voltage-controlled magnetic anisotropy that promise higher performance and also low write latency for MRAM technologies. I think that probably most applications are read intensive and so the read is the real place where the focus is, but it does look like we are going to get there.
Q: Are all the new Memory technology protocols (electrically) compatible to DRAM interfaces like DDR4 or DDR5? If not, then shouldn’t those technologies have lower chances of adoption as they add dependency on custom in-memory controller?
A: That’s just a logic problem. There’s nothing innate about any memory technology that couples it tightly with any kind of a bus, and so because NOR Flash and SRAM are the easy targets so far, most emerging technologies have used a NOR flash or SRAM type interface. However, in the future they could use DDR. There’re some special twists because you don’t have to refresh emerging memory technologies. but you know in general they could use DDR.
But one of the beauties of CXL is that you put anything you want to with any kind of interface on the other side of CXL and CXL erases what the differences are. It moderates them so although they may have different performances it’s hidden behind the CXL network. Then the burden goes on to the CXL controller designers to make sure that those emerging technologies, whether it’s MRAM or others, can be adopted behind that CXL protocol. My expectation is for there to be a few companies early on who provide CXL controllers that that do have some kind of a specialty interface on them whether it’s for MRAM or for Resistive RAM or something like that, and then eventually for them to move their way into the mainstream. Another interesting thing about CXL is that we may even see a hierarchy of different memories within CXL itself which also includes as part of CXL including domain specific processors or accelerators that operate close to memory, and so there are very interesting opportunities there as well. If you can do processing close to memory you lower the amount of data you’re moving around and you’re saving a lot of power for the computing system.
Q: Emerging memory technologies have a byte-level direct access programming model, which is in contrast to block-based NAND Flash. Do you think this new programming model will eventually replace NAND Flash as it reduces the overhead and reduces the power of transferring Data?
A: It’s a question of cost and that’s something that was discussed very much in our webinar. If you haven’t got a cost that’s comparable to NAND Flash, then you can’t really displace it. But as far as the interface is concerned, the NAND interface is incredibly clumsy. All of these technologies do have both byte interfaces rather than a block interface but also, they can write in place – they don’t need to have a pre-erased block to write into. That from a technical standpoint is a huge advantage and now it’s just a question of whether or not they can get the cost down – which means getting the volume up.
Q: Can you discuss the High Bandwidth Memory (HBM) trends? What about memories used with Graphic Processing Units (GPUs)?
A: That topic isn’t the subject of this webinar as this webinar is about emerging memory technologies. But, to comment, we don’t expect to see emerging memory technologies adopt an HBM interface anytime in the really near future because HBM does springboard off DRAM and, as we discussed on one of the slides, DRAM has a transition that we don’t know when it’s going to happen that it goes to another emerging memory technology. We’ve put it into the early 2030s in our chart, but it could be much later than that and HBM won’t convert over to an emerging memory technology until long after that.
However, HBM involves stacking of chips and that ultimately could happen. It’s a more expensive process right now – a way of getting a lot of memory very close to a processor – and if you look at some of the NVIDIA applications for example, this is an example of the Chiplet technology and HBM can play a role in those Chiplet technologies for GPUs.. That’s another area that’s going to be using emerging memories as well – in the Chiplets. While we didn’t talk about that so much in this webinar, it is another place for emerging memories to be playing a role.
There’s one other advantage to using an emerging memory that we did not talk about: emerging memories don’t need refresh. As a matter of fact, none of the emerging memory technologies need refresh. More power is consumed by DRAM refreshing than by actual data accesses. And so, if you can cut that out of it, you might be able to stack more chips on top of each other and get even more performance, but we still wouldn’t see that as a reason for DRAM to be displaced early on in HBM and then later on in the mainstream DRAM market. Although, if you’re doing all those refreshes there’s a fair amount of potential of heat generation by doing that, which may have packaging implications as well. So, there may be some niche areas in there which could be some of the first ways in which some of these emerging memories are potentially used for those kinds of applications, if the performance is good enough.
Q: Why have some memory companies failed? Apart from the cost/speed considerations you mention, what are the other minimum envelope features that a new emerging memory should have? Is capacity (I heard 32Gbit multiple times) one of those criteria?
A: Shipping a product is probably the single most important activity for success. Companies don’t have to make a discrete or standalone SRAM or emerging memory chip but what they need to do is have their technology be adopted by somebody who is shipping something if they’re not going to ship it themselves. That’s what we see in the embedded market as a good path for emerging memory IP: To get used and to build up volume. And as the volume and comfort with manufacturing those memories increase, it opens up the possibility down the road of lower costs with higher volume standalone memory as well.
Q: What are the trends in DRAM interfaces? Would you discuss CXL’s role in enabling composable systems with DRAM pooling?
A: CXL, especially CXL 3.0, has particularly pointed at pooling. Pooling is going to be an extremely important development in memory with CXL, and it’s one of the reasons why CXL probably will proliferate. It allows you to be able to allocate memory which is not attached to particular server CPUs and therefore to make more efficient and effective use of those memories. We mentioned this earlier when we said that right now DRAM is that memory with some NAND Flash products out there too. But this could expand into other memory technologies behind CXL within the CXL pool as well as accelerators (domain specific processors) that do some operations closer to where the memory lives. So, we think there’s a lot of possibilities in that pooling for the development and growth of emerging memories as well as conventional memories.
Q: Do you think molecular-based technologies (DNA or others) can emerge in the coming years as an alternative to some of the semiconductor-based memories?
A: DNA and other memory technologies are in a relatively early stage but there are people who are making fairly aggressive plans on what they can do with those technologies. We think the initial market for those molecular memories are not in this high performance memory application; but especially with DNA, the potential density of storage and the fact that you can make lots of copies of content by using genetic genomic processes makes them very attractive potentially for archiving applications. The things we’ve seen are mostly in those areas because of the performance characteristics. But the potential density that they’re looking at is actually aimed at that lower part of the market, so it has to be very, very cost effective to be able to do that, but the possibilities are there. But again, as with the emerging high performance memories, you still have the economies of scale you have to deal with – if you can’t scale it fast enough the cost won’t go down enough that will actually will be able to compete in those areas. So it faces somewhat similar challenges, though in a different part of the market.
Earlier in the webcast, we said when showing the orb chart, that for something to fit into the computing storage hierarchy it has to be cheaper than the next faster technology and faster than the next cheaper technology. DNA is not a very fast technology and so that automatically says it has to be really cheap for it to catch on and that puts it in a very different realm than the emerging memories that we’re talking about here. On the other hand, you never know what someone’s going to discover, but right now the industry doesn’t know how to make fast molecular memories.
Q: What is your intuition on how tomorrow’s highly dense memories might impact non-load/store processing elements such as AI accelerators? As model sizes continue to grow and energy density becomes more of an issue, it would seem like emerging memories could thrive in this type of environment. Your thoughts?
A: Any memory would thrive in an environment where there was an unbridled thirst for memory. as artificial intelligence (AI) currently is. But AI is undergoing some pretty rapid changes, not only in the number of the parameters that are examined, but also in the models that are being used for it. We recently read a paper that was written by Apple* where they actually found ways of winnowing down the data that was used for a large language model into something that would fit into an Apple MacBook Pro M2 and they were able to get good performance by doing that. They really accelerated things by ignoring data that didn’t really make any difference. So, if you take that kind of an approach and say: “Okay. If those guys keep working on that problem that way, and they take it to the extreme, then you might not need all that much memory after all.” But still, if memory were free, I’m sure that there’d be a ton of it out there and that is just a question of whether or not these memories can get cheaper than DRAM so that they can look like they’re free compared to what things look like today.
There are three interesting elements of this: First, CXL, in addition allowing mixing of memory types, again allows you to put in those domain specific processors as well close to the memory. Perhaps those can do some of the processing that’s part of the model, in which case it would lower the energy consumption. The other thing it supports is different computing models than what we traditionally use. Of course there is quantum computing, but there also is something called neural networks which actually use the memory as a matrix multiplier, and those are using these emerging memories for that technology which could be used for AI applications. The other thing that’s sort of hidden behind this is that spin tunnelling is changing processing itself in that right now everything is current-based, but there’s work going on in spintronic based devices that instead of using current would use the spin of electrons for moving data around, in which case we can avoid resistive heating and our processing could run a lot cooler and use less energy to do so. So, there’s a lot of interesting things that are kind of buried in the different technologies being used for these emerging memories that actually could have even greater implications on the development of computing beyond just the memory application themselves. And to elaborate on spintronics, we’re talking about logic and not about spin memory – using spins rather than that of charge which is current.
Q: Flash has an endurance issue (maximum number of writes before it fails). In your opinion, what is the minimum acceptable endurance (number of writes) that an emerging memory should support?
It’s amazing how many techniques have fallen into place since wear was an issue in flash SSDs. Today’s software understands which loads have high write levels and which don’t, and different SSDs can be used to handle the two different kinds of load. On the SSD side, flash endurance has continually degraded with the adoption of MLC, TLC, and QLC, and is sometimes measured in the hundreds of cycles. What this implies is that any emerging memory can get by with an equally low endurance as long as it’s put behind the right controller.
In high-speed environments this isn’t a solution, though, since controllers add latency, so “Near Memory” (the memory tied directly to the processor’s memory bus) will need to have higher endurance. Still, an area that can help to accommodate that is the practice of putting code into memories that have low endurance and data into higher-endurance memory (which today would be DRAM). Since emerging memories can provide more bits at a lower cost and power than DRAM, the write load to the code space should be lower, since pages will be swapped in and out more frequently. The endurance requirements will depend on this swapping, and I would guess that the lowest-acceptable level would be in the tens of thousands of cycles.
Q: It seems that persistent memory is more of an enterprise benefit rather than a consumer benefit. And consumer acceptance helps the advancement and cost scaling issues. Do you agree? I use SSDs as an example. Once consumers started using them, the advancement and prices came down greatly.
Anything that drives increased volume will help. In most cases any change to large-scale computing works its way down to the PC, so this should happen in time here, too. But today there’s a growing amount of MRAM use in personal fitness monitors, and this will help drive costs down, so initial demand will not exclusively come from enterprise computing. At the same time, the IBM FlashDrive that we mentioned uses MRAM, too, so both enterprise and consumer are already working to simultaneously grow consumption.
Q: The CXL diagram (slide 22 in the PDF) has 2 CXL switches between the CPUs and the memory. How much latency do you expect the switches to add, and how does that change where CXL fits on the array of memory choices from a performance standpoint?
The CXL delay goals are very aggressive, but I am not sure that an exact number has been specified. It’s on the order of 70ns per “Hop,” which can be understood as the delay of going through a switch or a controller. Naturally, software will evolve to work with this, and will move data that has high bandwidth requirements but is less latency-sensitive to more remote areas, while managing the more latency-sensitive data to near memory.
Q: Where can I learn more about the topic of Emerging Memories?
Here are some resources to review
- Persistent Memory Summit Presentations
- Blog post on the first FRAM, which was made in 1952, making it the first semiconductor memory: FRAM Turns 68
- Blog Post on Gordon Moore 1970 PCM paper: Original PCM Article from 1970
- Blog post with overview of all the emerging memory technologies: Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.
The lines are blurring as new memory technologies are challenging the way we build and use storage to meet application demands. That’s why the 
Many followers (dare we say fans?) of the SNIA Networking Storage Forum (NSF) are familiar with our popular webcast series “
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