Kurtis Bowman

The public release of the Gen-Z Core Specification 1.0 enables silicon providers and IP developers to begin the development of products enabling Gen-Z technology solutions. This presentation outlines how Gen-Z will address the multiple server challenges brought on by the explosion of data (180ZB annually by 2025) and the need for a high-speed, low-latency, scalable, memory-centric fabric. Customers have more data and require more processing of that data, and to be competitive, companies must monetize that data.

In this session we take a look at three powerful interconnect technologies. A brief overview is provided for all three: CCIX, Gen-Z, and OpenCAPI, each presented by industry experts. The focus will be on the current status of each interconnect, and how they are relevant to persistent memory. The panel will then answer questions from the audience.

This presentation discusses the interconnect requirements for highly performant persistent memory.

The CXL 3.1 specification introduces CXL fabric manager and extensions, Trusted-Execution-Environment Security Protocol (TSP), and facilitate memory sharing between accelerators and GPUs. This panel presentation will introduce the new features and explore how CXL attached memory to meet the increased memory capacity and bandwidth for HPC, AI, and ML applications in modern data centers. Expert representatives from CXL Consortium member companies will highlight ROI examples when implementing CXL attached memory.