As humanity embraces digital technologies at a rapid pace, data generation and consumption is growing at very high rate. In modern IT infrastructure, humongous amounts of data are being generated by various applications, devices and processes such as autonomous vehicles, social networks, genomics, and smart sensors. New AI and ML algorithms are being developed to effectively analyze the collected data and use it to achieve even greater efficiencies and productivity of applications.

I/O is recognized as a performance bottleneck in HPC domains. This is expected to worsen with increase in the disparity between computation and I/O capacity on future HPC machines. The fundamental consideration for all potential technologies and architectures is the trade off between cost and performance.

Our talk highlights our experience in prototyping heterogeneous memory tiering for CacheLib. CacheLib is a general-purpose caching engine developed by Meta with support for hybrid caching using DRAM and flash. prototype adds transparent application-level support of heterogeneous memory. We describe the techniques used to reduce the overhead of data movement among heterogeneous memory tiers and the current challenges we encounter today.