The requirement for ever denser memories is answered by the introduction of new NAND memory technologies. New multi-layer three dimensional stacking (BiCS4) as well as four bits per cell (QLC) technologies are introduced by the NAND memory FAB companies. The introduction of these technologies brings into bear reliability challenges which are answered with new and unique methods. Any memory controller must contend with the variability between the layers in 3D manufacturing technologies as well as the high error rates and stress condition sensitivity introduced by QLC.

Challenges facing system designers, mother board designers are: Space, Performance and Cost. Increasing the data-rate of electrical interfaces on PCB, increases cost of manufacturing and add to other engineering challenges. Dedicated pins on the CPU sockets for DDR like interfaces are limited.

In most architectures, data is copied from far memory or storage to a local memory for processing. However, when the size of data is in order of hundreds of gigabytes, it is efficient to move static compute functions near data, instead of copying the bulky data near compute.

For a long time, using software to perform memory copies has been the gold standard for applications performing memory-to-memory data movement or system memory operations. The newly released SNIA Smart Data Accelerator Interface (SDXI) Specification v1.0 attempts to change that.