SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Abstract
A generation of new non-volatile memories (NVMs) potentially capable of working with, or replacing, SDRAM are in design now. Memory controller designers will want to exploit the advantages of these new memories, such as zero-power standby and the elimination of content refresh. JEDEC is in the process of defining the DDR5 NVRAM specification, the first of the detailed definitions of these new NVMs, as an enablement for systems designers to learn about and be ready for the coming wave.
Learning Objectives
understand value of persistent memory,multiple memory architectures in one specification