SNIA Developer Conference September 15-17, 2025 | Santa Clara, CA
Abstract
A variety of persistent memory technologies with DRAM-class performance, known as “memory class storage” or “MCS”, have appeared on the horizon. MCS will change the architecture of future computing systems. These technologies include carbon nanotube memory, phase change memory, magnetic spin memory, and resistive memory, and each has unique characteristics that can complicate systems designed to exploit them. The JEDEC DDR5 NVRAM specification in process intends to bridge the differences between the technologies and provide systems designers with a unified specification for DRAM-class persistent memory. Nantero NRAM is a NVRAM based on carbon nanotube cell structures that provides a DDR4 or DDR5 interface to the system, and provides additional enhancements to yield 20% higher performance at the same clock rate.