SNIA Developer Conference (SDC)

Facundo is currently the tech lead for Dropbox's exabyte-scale blob storage system. These teams manage everything from customized storage machines with many petabytes of capacity to the client APIs other teams use internally. Prior to working at Dropbox, Facundo worked at Amazon on a variety of scheduling problems for Amazon's last mile delivery team.

Richelle Ahlvers runs Technology Initiatives and Ecosystem Enabling for the Datacenter and AI business for Intel, promoting and driving enablement of new technologies and standards strategies. Richelle has spent over 30 years in Enterprise R&D teams in a variety of technical roles, spanning architecture, design and development of software, firmware, and hardware, for everything from enterprise storage solutions to CPUs. Richelle has been engaged with industry standards initiatives for many years and is actively engaged with many groups including SNIA, DMTF, NVMe, OFA and UCIe. She is Vice-Chair of the SNIA Board of Directors, Chair of the Storage Management Initiative, leads the SSM Technical Work Group developing the Swordfish Scalable Storage Management API, and is a former SNIA Technical Council Chair. She serves on the DMTF Board of Directors as the VP of Alliances.

Mike Allison is a Sr. Director in the Samsung Semiconductor Product Planning and Business Enablement team focusing on standards for existing and future NAND products. He is a participating member of SNIA, NVM Express, DMTF, PCI-SIG, and OCP. He is a member of the NVMe Board of Directors, chair of the NVMe Errata Task Group, and represents the OCP Storage Project on the OCP Steering Committee. Over a 41-year career, Mike has been an embedded firmware engineer and architect on products for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 38 patents and earned a BSEE/CS at University of Colorado, Boulder.

Jens Birk Andersen is a PhD Industrial Researcher with the GOST team at Samsung Electronics and an Industrial PhD Fellow at the IT University of Copenhagen (ITU). His research operates at the intersection of computer systems and machine learning, with a specific focus on storage hierarchies, I/O paths, and data movement in deep learning workloads.

Brian Atkinson is a HPC Engineer at Los Alamos National Lab in the HPC-DES. His research is focused on next generation storage systems at LANL. Brian has worked on building fast storage endpoints, which leverage new and emerging storage technologies. He has made contributions to various open-source file system projects. He led the source code development of adding Direct I/O support to ZFS. His work has focused on improving performance and efficiencies with distributed file systems.

Curtis Ballard is a Distinguished Technologist with Hewlett Packard Enterprise in the HPE Storage organization where he works on storage architecture, intellectual property, and storage technology strategy with a focus on enabling new storage technologies. Curtis has 30 years of experience in storage and storage interfaces technologies where he has worked in product design teams for storage arrays, storage enclosures, tape drives, tape libraries, and magneto optical drives. He has developed hardware designs for storage interfaces and storage controllers as well as firmware for motion control, storage interfaces, user interface, and embedded operating systems. In addition to Storage Platform development for HPE, Curtis also represents HPE in several industry organizations. Curtis is a treasurer for the NVM Express Board of Directors, is a member of the SNIA Technical Council, and is the vice-chair of the INCITS/SCSI (T10) Storage Interfaces Technical Committee where he has been the editor for several SCSI standards. He is an inventor on over 40 US patents in the storage industry across electrical, software, and mechanical disciplines.

Stephen Bates is an Fellow in the AI Business Unit at AMD, where he leads work on communication and storage architectures and associated software for AI and data-centric systems. He is a recognized expert in high-performance technologies including NVMe, RDMA, TCP/IP, and non-volatile memory, with deep experience developing complex storage and communication solutions such as NVMe controllers and PCIe switching fabrics.

Stephen thrives at the intersection of hardware and software, bridging architectural innovation with practical implementation. He is an active contributor to the Linux kernel and other open-source projects that advance system performance and scalability.

Prior to AMD, Stephen served as Assistant Professor of Computer Engineering at the University of Alberta. He holds a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Filip Blagojevic is a Research Scientist at Western Digital. His research focuses on storage systems, high-performance computing, distributed systems, and system-level optimization for data-intensive workloads. He received his PhD in Computer Science from Virginia Tech in 2008 and previously worked at Lawrence Berkeley National Laboratory. 

His recent work explores storage and systems support for emerging AI workloads, including LLM inference, KV-cache management, and memory/storage tiering. He has also worked extensively on Linux file systems, HDD-SMR storage, Hadoop/HDFS, erasure coding, and performance characterization of large-scale storage systems.

Ralph Böhme is a member of the international Samba Team and leads the Samba team at SerNet.

Rory joined KIOXIA America in 2017. He has founded, built teams, and delivered product at four storage startups which were acquired ($400M, $165M and two undisclosed). Rory has more than twenty-five years of experience in data storage systems, data protection systems, and high performance computing with tenures as VP software Engineering at Samsung, Technical Director/CTO counsel at NetApp, CTO counsel at EMC, Vice President, Chief Storage Architect, and Distinguished Fellow at Quantum. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.

Thomas Boone, Ph.D. is a Distinguished Engineer at Western Digital where he manages defense and aerospace research program. He leads the company’s performance of the United States Air Force Research Lab ANGSTRM program to develop the next-generation strategically rad-hard memory for the DoD. With over 20 years experience in R&D management and technical leadership within the microelectronics and data storage industries, he specifically focuses on HiRel rad-hard microelectronic solutions for defense and aerospace applications. Dr. Boone received his Ph.D. in AP/EE from Yale University in 2004, MSEE from Purdue University in 1998 and BSEE from U.T. Arlington in 1994. He has over 20 issued U.S. patents and co-author of 26 peer-reviewed journal articles.

Jeff Bromberger is a Windows kernel programmer.

Satananda Burla is a Distinguished Engineer at Marvell, involved in the design and development of Marvell Octeon SoC architecture. He is also involved in the design and development of Networking, Memory/Storage, and Security solutions involving multiple Marvell product lines. He represents Marvell at OPI, OASIS, IBTA, UEC, and other technical forums.

Dr. Yu-Ming Chang has served as Director at Wolley since 2016, leading technology and product development in storage class memory (SCM) controllers and NVMe-over-CXL solutions. Prior to joining Wolley, he was a manager at the Emerging System Lab of Macronix Taiwan and a technical consultant for the National Security Bureau. Dr. Chang has published over 50 technical papers at leading international conferences, including DAC, ICCAD, and ISLPED. He holds more than 40 patent applications, with 23 patents granted. He received his Ph.D. in Computer Science and Information Engineering from National Taiwan University.

Tejas Chopra is Sr. Engineer at Netflix, where he works as part of the ML/AI platform building the offline training storage tier - called Axion. Tejas is also the creator of Headroom - a context optimization platform for AI Agents. He is the co-author of a systems design book (Packt) and has authored LinkedIn Learning courses on ML model optimization. He co-presented at SDC 2023 on the intersection of storage architecture and AI systems, and is a frequent speaker on distributed systems, caching, and ML infrastructure.

Anthony Constantine is a Distinguished Member of Technical Staff responsible for Storage Standards at Micron. He is very active in SNIA as co-chair of the SFF TWG, an author for several EDSFF specifications, and author or contributor to several other SFF TWG specifications. He is also a past member of the SNIA Technical Council. In addition, Anthony contributes to PCI-SIG, JEDEC, NVMe, and Open Compute Platform (OCP). Anthony has over 25 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Clarete Crasta is a Principal Engineer in Hewlett Packard Enterprise, currently working in the HPC and AI Advance Development group. She is a well-recognized technical architect and has built a solid reputation over 20 years with deep system software expertise in High Performance Computing, memory and storage technologies, operating systems kernel, platform & IO, and virtualization. Her ability to drive and lead teams, focus on customers, willingness to take up any complex work in newer areas, effective communication skills, and active collaboration has gained her acceptance across the community. Clarete has experience leading and collaborating across teams, business units, customers and partners. She is a co-inventor on 13 US filed patents and has co-authored 7 publications. She has presented at various conferences such as SNIA CMS, SNIA SDC, CUG, GHCI on Fabric Attached Memory and related topics. She has worked as a member of the technical committee and review board for GHCI, IEEE and is serving as Industry Track Chair for IC2E. She holds a master’s degree in software engineering and bachelor’s in electrical engineering.

Improve data, network and physical security. He also works to help teams across HPE develop pragmatic techniques for machine learning, data access and building very large-scale systems. He has a long history building startups in machine learning and large data systems including MapR, Veoh Networks, ID Analytics and MusicMatch. He also has a strong background in open-source software, serving on the board of directors at the Apache Software Foundation and the Presto project at the Linux Foundation. Ted’s primary focus is on developing technologies that are groundbreaking but also simple enough to understand, deploy and maintain over the long term. This focus has resulted in new techniques for recommendations, fraud and error detection, and data sketches. His recent work is on building systems that allow coherent data security across different storage and identity platforms Ted has a Ph.D. in Computer Science from the University of Sheffield, UK. He is co-author of more than 10 books focused on data sciences. He has over 25 patents related to recommendations, search, coding theory, data storage and streaming data.

Frank Ferro is the group director of product marketing at Cadence Design Systems responsible for memory interface IP products. Frank joined Cadence after spending 25+ years at Rambus, AT&T, Lucent, and Agere Systems. Mr. Ferro holds an executive MBA from the Fuqua School of Business at Duke University, an M.S. in computer science, and a B.S. in electronic engineering technology from the New Jersey Institute of Technology.

Vincent Franceschini is an accomplished strategist and technologist with over 30 years of experience shaping products and solutions in IT and data storage. He is today the Senior Director of Product Management at Biomemory, pioneering synthetic DNA-based storage for next-generation data centers. Previously, he was Chief Research Officer at Hitachi Vantara, leading co-innovation initiatives with customers and partners. Within the Hitachi Group and industry consortia, he contributed to technology and standards initiatives across AI, telecom, manufacturing, logistics, HR-tech, and IT & data storage domains. Vincent has led projects in Europe, the US, Japan, and China, served nine years on the SNIA Board including two as Chairman, and is now SNIA Chairman Emeritus and Co-Chair of the DNA Data Storage Alliance. Franceschini began his career in technology at Digital Equipment Corporation as a software engineer. He received his “Ingénieur en Informatique” degree in Artificial Intelligence & Industrial Applications from l’École Pour l’Informatique et les Techniques Avancées in Paris, France.

Steve French is a member of the Samba team, and Principal Software Engineer at Microsoft (Azure Storage), and long time maintainer (as well as original author) of one of the more active Linux file systems (cifs.ko), and a frequent presenter at SMB and storage conferences. He is also co-maintainer of the Linux kernel server (ksmbd). He was formerly chair of the SNIA CIFS Working group and co-author of the SNIA CIFS Specification. Formerly he was File System Architect for the IBM Linux Technology Center.

John Geldman leads the storage standards engagements of Kioxia. He has been contributing to standards for five decades. John has dabbled in NAND & Spinning Storage, Linux & VxWorks internals, Networking, Security, and IC development (and Daisy Wheel printers). John’s storage experience started with SASI and ST-506 designs a long time ago John currently sits on the SNIA Board of Directors, Chairs the SNIA Alliance Committee, and co-Chairs the NVMe-MI Task Group. John continues to contribute to these organizations: NVM Express, PCI-SIG, SNIA, JEDEC, SCSI/T10, ATA/T13, IEEE SiSWG, & TCG. John has been on the board, an officer, a chair, and/or edited specifications for: CompactFlash, SD Card Association, USB, UFSA, IEEE 1667, JEDEC, SCSI/T10, & ATA/T13.

David Gerstein is the founder and CTO of Leil Storage and the founder of Diaway. With over a decade of experience in data storage, he is a recognized expert in scalable and efficient storage systems. At Leil Storage,David is driving the development of HDD-Native™ storage solutions purpose-built for the SMR era.

Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.

Stephen Gold is a SSD portfolio architect, driving architectural solutions for Sandisk's next-generation enterprise SSD product line. Stephen also drives Sandisk's enterprise ecosystem strategy, working with partners and enterprise SSD customers to imagine and architect new solutions to solve tomorrow's storage problems.

Jason is a Distinguished Engineer at Dell Technologies, working in the Storage Chief Technology Office. His role involves leading the development of next-generation storage and network protocols for both Public and Private Clouds. Jason also serves as Chair of the SNIA Accelerated Object I/O Technical Working Group. Throughout his career, Jason has focused on enterprise storage and meeting the needs of customers who want to expand beyond the traditional on-premises data center. He enjoys collaborating with customers and partners to understand their requirements when transforming their business. In his personal life, Jason is passionate about running marathons and baking artisan bread. He lives in Newton, Massachusetts, with his wife and their three children.

Alessandro Goncalves is a Storage Solutions Architect specializing in high-performance storage systems, AI/ML infrastructure, and workload-aware performance engineering. Currently at Solidigm, he focuses on architecting and benchmarking SSD-based solutions for emerging AI and inference workloads, collaborating with organizations such as MLCommons to evaluate next-generation storage behavior for data-intensive AI pipelines. His background includes persistent memory architecture and performance engineering work at Intel, where he contributed to solutions involving Optane and large-scale storage performance analysis across enterprise and hyperscale environments. His recent work centers on AI-oriented storage observability, workload fingerprinting, vector database benchmarking, KV-cache infrastructure, and cross-layer latency attribution for modern storage systems.

Adam Gray is Principal Software Engineer at IBM Cloud Object Storage and has nearly 15 years of experience in object storage. Adam primarily works in distributed systems, hyperscale computing, and mentoring students and new hires. Adam has 40+ patents issued by the USPTO and is an IBM Master Inventor. He earned his B.S. in Computer Science from Indiana University and lives and works from Chicago, Illinois.

Chandra Guda is a Senior Member of Technical Staff (SMTS) System Architect based in San Jose, California, where he focuses on storage next architectures for GPU‑accelerated and high‑performance computing workloads. His current work spans NVMe, AI workloads and studying heterogeneous CPU–GPU data paths, with an emphasis on scalable, low‑latency, and secure storage systems. He previously held roles in firmware architecture and staging technologies at WDC and developed firmware for SSDs, HDDs. He holds a Masters Engineering degree and brings over two decades of experience in system architecture and storage technologies and hold 30+ Patents in Storage architecture technology.

Jack Guedj is co-founder and CEO of Numem, Inc., a provider of low-power Memory/SOC Subsystem IP Cores (based on MRAM), Chiplets and Turnkey Custom Chips. Beginning in 2008, Jack was President and CEO of Tensilica, leading it to the #1 position in merchant DSPs and, the acquisition by Cadence in 2013. Jack was then Cadence Corporate VP, Tensilica Products. Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic, serving as founder, president and CEO. Prior to Cirrus, he was president of Tvia, Inc., leading that company's successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management, an MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie.

Kalyan Gunda is a Senior Distinguished Engineer and Chief Architect for Unstructured Storage at Dell Technologies, focused on scalable object storage and distributed data platforms. He brings deep expertise across S3/object storage, distributed file systems, and data protection, helping enterprises simplify data infrastructure for modern, data‑intensive workloads. Kalyan works at the intersection of storage and AI, shaping how application‑driven, API‑first storage models enable scalable data pipelines for next‑generation workloads.

Abhishek Gupta is a Storage Architect at Cerebras Systems, where he designs next-generation storage infrastructure for large-scale AI training and inference workloads. He brings over 15 years of experience building distributed storage systems, file systems, and high-performance I/O stacks. Previously, he worked as Senior Staff at Huawei's Research Centre, with earlier principal and senior engineering roles at Dell EMC (Isilon OneFS, Data Domain), DDN, NetApp, and Veritas. His work spans GPU Direct Storage, File-over-Memory, CXL, computational storage, and distributed file systems.

Jonmichael Hands is CEO of FarmGPU and AI Technologist at Solidigm, where he focuses on the intersection of storage, AI infrastructure, and emerging workloads. He brings over a decade of experience from Intel’s Non-Volatile Memory Solutions Group, where he led product line management, strategic planning, and technical marketing for data center SSDs. Jonmichael has held key industry leadership roles, including Chair of NVMe Marketing and Co-Chair of the SNIA SSD Special Interest Group, and has contributed to storage and sustainability initiatives within the Open Compute Project. He previously served as VP of Storage at Chia Network and remains an advisor. Jonmichael is Chairman of the Board of the Circular Drive Initiative (CDI), a 501(c)(6) organization advancing secure drive reuse and circular business models across the storage industry. He began his career at Sun Microsystems designing storage arrays (JBODs) and holds a degree in Electrical Engineering from the Colorado School of Mines.

Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became highly respected as an analyst for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com. His reports can be purchased at www.Objective-Analysis.com

Erich Haratsch is Senior Distinguished Engineer at Marvell, where he leads architecture definition for SSD and storage controllers. 

Before Marvell, he worked at Seagate and LSI on SSD and HDD controllers across multiple product generations, and earlier at Agere Systems on HDD controller development. 

He began his career at AT&T and Lucent Bell Labs, contributing to Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. 

Erich is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. 

He is a Senior Member of IEEE and holds MS and PhD degrees from the Technical University of Munich, Germany.

Eric A. Hibbard is the Director, Product Planning – Security at Samsung Semiconductor, Inc. and a cybersecurity and privacy leader with extensive experience in industry, U.S. Government, and academia. He is active in cybersecurity, privacy, storage, cloud, AI, and IoT standards and industry organizations. Mr. Hibbard serves as the Chair of INCITS/Cybersecurity & Privacy, the IEEE Cybersecurity & Privacy Standards Committee, and the SNIA Security Technical Work Group (TWG) as well as leadership positions in ISO/IEC, the American Bar Association, and the Cloud Security Alliance. He has served as author/editor for key standards, including ISO/IEC 27040, ISO/IEC 27050 series, ISO/IEC 22123 series, NIST SP 800-88r2, and NIST SP 800-209r1. Mr. Hibbard possesses a unique set of professional credentials that include the (ISC)2 CISSP-ISSAP, ISSMP, and ISSEP certifications; IAPP FIP, CIPP/US and CIPT certifications; ISACA CISA and CDPSE certifications; and CSA CCSK certification. He has a BS in Computer Science.

Jonathan Hinkle is Senior Director of Storage Pathfinding at Solidigm, where he leads strategy and innovation for next generation storage used in AI, compute, and data storage infrastructure. He previously held a similar leadership role at Microsoft, guiding Azure’s memory and storage architecture pathfinding. With over 25 years of experience at companies including Micron, Lenovo, and IBM, he is an industry leader in system architecture spanning SSDs, DRAM, and persistent memory. He is also active in industry standards, helping drive alignment and adoption across the global technology ecosystem.

Jason Holpuch is the Hardware Technologist owning server architecture, NPI, vendor management, and supply chain for GEICO's datacenter infrastructure.  Jason's previous experience and roles span, autonomous vehicle hardware, hyperscale storage, nvme and storage development, and aerospace industries.

Chih-Tsung Huang is the Senior Director of Hardware Engineering in the Common Hardware Group. Chih-Tsung is responsible for delivering Sustainable AI infrastructure solutions for silicon, hardware systems and optics in Cisco’s switching, routing, optical, access and IoT portfolios. Chih-Tsung has over 100 US and Global patents covering a breadth of topics including but not limited to sustainability, silicon, FPGA, networking, compute, security and storage.

Neil Hutchison is a SSD System Architect with deep expertise in performance architecture driving architectural solutions for Sandisk's current and next-generation enterprise SSD product line. Neil is the co-chair for the SNIA Solid State Storage Technical Working Group driving industry standards for performance testing in both Client and Enterprise SSD's.

Hansen Idden is a third-year PhD student at Virginia Tech researching CXL-based storage and memory systems. He has published at FAST and ASPLOS on CXL-SSD emulation and memory tiering. His current research focuses on characterizing commercial CXL-SSD devices to understand buffer management behavior and inform workload optimization strategies.

20 years of experience working on parallel file systems

Randy Jennings has been involved in the storage industry for over twenty years starting with implementing a Fibre Channel protocol analyzer as an intern at Data Transit, through implementing the Infinite Volume distributed filesystem for NetApp, and writing Pure Storage's first NVMeoF implementation for a storage shelf. He currently works to increase adoption of NVMeoF by increasing the enterprise readiness of the NVMeoF protocol and implementations of it. He was one of the primary authors of NVMe Technical Proposal 4129 and Technical Proposal 8028 which address data corruptions and recovery times after a loss of communication.

Klaus is a principal software engineer with Samsung Semiconductor Denmark Research where he leads a small, dedicated team tasked with technology adoption and enablement of emerging technologies in the open ecosystem. He is involved with the NVMe® community as a technical proposal co-author and as an alternate on the Board of Directors and maintains the QEMU emulated NVMe® device and the libvfn user-space NVMe® and PCIe® driver library.

Thomas Jew is a Fellow at NXP and leads development of Non-Volatile Memory solutions for Advanced Microcontroller and Microprocessor applications. He has worked on discrete non-volatile memory products and embedded memory designs including traditional flash and emerging memory technologies integrated in microcontrollers for IOT and Automotive applications for 35+ years. Prior to joining NXP by way of Freescale Semiconductor/Motorola, he worked for Texas Instruments, designing discrete flash memories. Thomas received his BS and MS degrees in Electrical Engineering from Texas A&M University in 1988 and 1991 respectively.

Howard is the chair of the INCITS/Fibre Channel techncial committee and remains actively involved in the development of Fibre Channel standards. As Broadcom's technical liaison to many Fibre Channel industry partners, Howard joined the forces of the Fibre Channel ecosystem vendors to deliver products based on the Fabric Notifications standards and architecture for the Fibre Channel industry. These efforts developed solutions that leveraged Fabric Notifications in the formation of autonomous SAN technology. Howard began his career in 1984 developing configuration applications for 3270 Cluster Controllers for McDATA Corporation in Boulder, Colorado. In 1993, in partnership with IBM, Howard was part of the team that created the ESCON Director Models 3/4/5 as well as the FICON to ESCON Bridge. As technical leader, he directed the efforts of the technical teams that expanded IBM’s original storage-area networks (SAN) from ESCON to FICON. In 2007, Howard joined Brocade, a Broadcom company, as a member of the Fabric Operating Systems Architecture group and is responsible for the technical strategy relating to Brocade’s mainframe infrastructure offerings. His industry experience lead to a featured interview in Enterprise Executive (2019, issue 6), where he discussed the future of the mainframe, FICON, and Fibre Channel. Today, Howard is an active member of the Brocade SAN Networking (BSN) division of Broadcom Limited and continues his technical leadership in enterprise networking solutions. With more than 40-years of professional experience in high-end processing environments, Howard remains an active advocate of Fibre Channel.

Trent Johnson is a Hardware Architect at IBM, with a focus on the IBM FlashCore Module (Solid State Drive). He joined IBM as part of the Cleversafe Acquisition where he was the System Hardware Architect of exabyte-scale Object Storage. Prior to Cleversafe, he developed system-level manufacturing and test solutions for AMD CPUs and GPUs where he was awarded the AMD Corporate Technical Achievement Award. 
He has 27 years of industry experience, holds 7 US patents and has published at the Future of Memory and Storage, SNIA Developer Conference, Burn-in and Test Socket Workshop as well as the Conference for Consumer Electronics. He earned BSEE and MSEE degrees from The University of Texas at Austin in Electrical Engineering with a focus on Manufacturing System Engineering.

Dingyi Kang is a third-year PhD student at the CS department of University of Texas at Dallas. His research focuses on the storage systems for approximate nearest neighbor search in AI/ML.

Kapil Karkra is a Sr. Principal Engineer at Solidigm responsible for software and solutions pathfinding for next-generation storage solutions supporting AI infrastructure. His work focuses on evolving Cloud Storage Acceleration Layer (CSAL), a host-based FTL with RAID and Caching, bringing technologies such as Mixed Media (MM) and Flexible Data Placement (FDP) to market, and defining turnkey reference architectures that integrate hardware and software to accelerate adoption of high-density NAND SSDs (QLC, PLC, and HLC) for AI workloads. Over his 25+ year career, he has advanced storage systems ranging from RAID, caching, and FTLs to distributed storage stacks at IBM, Intel, and Solidigm. Recently, he helped build AI cloud storage services at Intel, integrating technologies such as VAST Data Platform and MinIO AIStor. He has 35+ patent filings and 20+ issued patents, has authored numerous industry publications, and has contributed to industry standards including NVMe (e.g., Multiple Atomicity) and PCIe (e.g., Native PCIe Enclosure Management, NPEM). Kapil holds a bachelor's degree in electrical engineering from the National Institute of Technology (NIT), India, and an MBA from Arizona State University.

Sagar Kewalramani is a seasoned technology leader with 15+ years of success in designing, architecting, and deploying enterprise-scale Data and AI solutions for the world’s leading companies. Currently serving as Director of AI Platform Engineering and Field CTO within Dell’s CTO organization, he leverages deep technical expertise and strategic business acumen to spearhead the development of next-generation AI platforms and guide customers on their digital transformation journeys. Expert in Generative AI and agentic frameworks, RAG architectures, multi-agent orchestration, fine-tuning foundation models, and deploying scalable inference systems on GPU-accelerated infrastructure. Extensive experience designing modern data paradigms including Data Mesh and Data Lakehouse, with expertise in unified, hyperscale data platforms, streaming systems, and enterprise data governance ensuring robust data quality, lineage, and accessibility across multi-cloud environments. A “player-coach” with a demonstrated history of mentoring and leading high-performing, globally distributed engineering teams. Trusted C-suite advisor driving technical strategy, influencing product roadmaps, and enabling successful AI adoption at scale. Proven success in pre-sales leadership, consistently exceeding ambitious revenue targets, building strategic alliances with GSIs, ISVs, and technology partners, and creating powerful co-sell motions. Recognized thought leader and public speaker at major industry conferences, passionate about democratizing AI technology and mentoring the next generation of data and AI professionals.

Sanil has over 2 decades of product development expertise. He founded Caze Labs, building AI products in infrastructure cost observability and hiring domains. He researches on Agentic AI, contexts, and using MCPs for various data sources. He incubated open source projects and has patents/research papers to his credit. He is an industry-awarded technologist, played key roles at CNCF, SODA, IEEE, CCICI, and various open source projects(TOC, Program Committee, Governing Board, Maintainer). https://www.linkedin.com/in/sanilkumard/

Volker Lendecke is co-founder of SerNet GmbH in Göttingen, Germany and member of the Samba Team.

I'm a Linux kernel maintainer specialising in network file systems and high-performance storage protocols, with deep expertise in NFS and RDMA. My work focuses on the low-level infrastructure that enterprise and cloud storage depends on -- from kernel implementation to published standards. As co-maintainer of the Linux in-kernel NFS server, I'm responsible for code review, patch integration, and the ongoing health of one of the kernel's most widely-used subsystems. I've also authored or co-authored 11 IETF RFCs spanning NFS, RPC-over-RDMA, RPC encryption, and federated file systems -- including RFC 8166 (RDMA Transport for RPC) and RFC 9289 (RPC Encryption by Default).

Ivan Lobachev is a Technical Marketing Engineer at Solidigm, where he focuses on driving awareness and adoption of advanced storage technologies, with a particular emphasis on storage for AI and next-generation I/O technologies. He holds a PhD in Computer Science with an emphasis on distributed systems and machine learning, bringing deep technical expertise to his work in communicating the value of emerging storage solutions. Ivan is an active participant in key industry standards bodies, including NVM Express and PCI-SIG, where he contributes to the development of the PCIe specification. Over his 10+ years in the industry, primarily in storage, Ivan has built a strong foundation across the technology stack — from silicon-level innovation to cloud-scale infrastructure. His career includes experience at Intel and AWS, giving him a broad perspective that spans semiconductor, enterprise storage, and hyperscale cloud environments.

Simon A. F. Lund is a Principal Engineer at Samsung, where he leads the Systems Advancement and Integration (SAI) group and the Accelerator-integrated Storage I/O (AiSIO) project. His work focuses on system-software architectures that bridge compute and storage, informed by a background spanning storage systems engineering and research on high-performance compilers, runtime systems, and hardware architectures for massively parallel compute in array-oriented programming. He is also the lead developer of the open-source xNVMe project and holds a Ph.D. from the University of Copenhagen.

Grant is a Distinguished Engineer at XCENA. Previously he was the CTO at Jackrabbit Labs, a CXL software and fabrics company,  Western Digital/Sandisk, and Los Alamos National Lab.  He is an industry veteran familiar with data center, storage, and memory fabric architectures, and has advanced these areas in one way or another through simulation, prototype, and productization efforts across his career.

Keith MacLean is a Member of Technical Staff and System Architect at Micron Technology, where he focuses on enterprise SSD architecture, power efficiency, and next-generation storage platform design.

Pankaj Mehra is Professor of Research in Computer Science and Engineering department at The Ohio State University. He founded Elephance Memory, a company that builds software to optimize disaggregated data center memory for data infrastructure and applications. Pankaj has held executive positions in the Memory industry since 2013 when he took over as SVP and WW CTO of Fusion-io, later serving as VP and Senior Fellow at both acquirers SanDisk and Western Digital. Pankaj Mehra led SmartSSD (as VP of Product Planning) and other workload-optimized flash storage products (as VP of Storage Pathfinding) at Samsung, for which he and his team of 10 received Samsung's prestigious R&D Award in 2019. SmartSSD went on to win the CES R&D Innovation Award in 2021. Previously at Hewlett-Packard, Pankaj was promoted to HP Distinguished Technologist in 2004 for his pioneering work on RDMA-attached persistent memory devices and filesystems. Later he founded HP Labs Russia and served as its Chief Scientist until 2010. He is also the founder of startups IntelliFabric, Whodini and AwarenaaS. Pankaj's international experience spans academia, industry and government. His publications include 3 books and over 100 papers and patents. Pankaj holds Ph.D. in Computer Science from The University of Illinois at Urbana-Champaign.

Rohan Mehta is a Member of Technical Staff and Systems Performance Engineer at Micron Technology, where he works on the Data Center Workload Engineering team. Since 2025, his work has focused on application‑level tracing, performance characterization, and data analysis to inform next‑generation SSD architecture and optimization for hyperscale and enterprise workloads. He also serves as Vice‑Chair of SNIA’s DSN Forum, where he helps conduct educational webinars, and industry tech talks that provide leadership and practical guidance on end‑to‑end storage and data networking solutions.

Previously, Rohan was a Senior Software Engineer at Microsoft, contributing to Azure Storage. There, he developed high‑performance storage‑over‑RDMA solutions for managed disks, led DPU offload proof‑of‑concepts for front-end and table layer of cloud storage stack, and worked closely with platform architecture teams to evaluate system‑level performance, scalability, and cost efficiency of next-gen Storage-for-AI buildout.

He holds an M.S. in Electrical Engineering from Columbia University and an M.Sc. (Honors) in Physics from BITS Pilani.

Stefan Metzmacher is working for SerNet and is a member of the international Samba Team. His focus is spread into all areas of Samba including WINS-Replication, DRS-Replication, Authentication, SMB*, DCERPC and a lot of architectural [re-]designs of common code.

Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives HPC strategy and the technical IO roadmap in NVIDIA GPU Cloud, focused on pushing the envelope for storage and networking programming models at scale, data center architecture and security, and scaled systems. 

He is a community builder with a passion for building an ecosystem that extends the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. 

He co-leads the Storage-Next effort to optimize products for IOPs/TCO. He tinkers with and leverages NVIDIA and vendor products in a lab packed with scaled compute, storage and networking gear to apply and extend new tech. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.

Aaron is a Technical Fellow working in the Microsoft Azure Core Team. 

He works (with many others) on optimizing the co-design of Hardware and Software for Azure Storage, Compute and Networking. 

Aaron has been working on Azure Storage since its inception in 2008 and has helped Microsoft optimize storage design and deployment, and has worked with industry partners to optimize components, servers and switch designs for the cloud. Aaron has helped influence the evolution of Network Switches, SSDs, HDDs and Archival Systems for Cloud deployment. 

Aaron started at Microsoft in 1991, and before Azure worked on a few notable projects, including Windows 95, DirectX, XBOX and Forza Motorsport. Aaron has a regional SCCA racing championship in Formula Mazda, which was instrumental in helping make Forza the highest grossing racing franchise on XBOX. Aaron also plays a little poker from time to time. He finished second in a World Poker Tour Tournament at a Televised Final Table.

Sergei Platonov is the Vice President of Strategy at Xinnor, a technology company specializing in storage solutions. Sergei's journey in the tech industry began in 2010 when he graduated from the university, earning a degree in Computer Science. With a strong passion for storage technologies, he joined SDS start-up in 2009. Throughout his career, Sergei has been instrumental in the development of Storage Area Networks (SAN) and has focused on the research and implementation of cutting-edge technologies such as Flash, NVMe (Non-Volatile Memory Express), CXL (Compute Express Link), and storage performance improvement techniques. His expertise in these areas has enabled Xinnor to create highly efficient and reliable storage solutions that cater to the evolving needs of businesses. Sergei's contributions to the industry go beyond development work. He is a recognized thought leader and has delivered more than 30 presentations at conferences, sharing his insights and knowledge on storage technologies. Additionally, he has authored numerous articles, shedding light on the advancements in Storage Class Memory and its impact on storage performance.

Swarna is a System Software Engineer at Samsung, building expertise in storage systems across both kernel and application layers. Their work focuses on enabling Samsung hardware by contributing to open source software focused on storage domain(scsi/NVMe). Previously, she was working at Intel as System Software Engineer working on integration and enablement of Chrome OS stack on Intel platforms. She holds a Masters degree in Computer Engineering from Texas A&M University.

Rohan Puri is a Senior Staff Engineer at DataDirect Networks (DDN), working on the Infinia IO Path. Previously he was a Staff Engineer at Samsung Semiconductor working on distributed file systems. He has worked across the Linux storage stack for over 15 years, including filesystem development at Oracle, Veritas, and contributions to OpenZFS. He holds a Masters in Computer Science from Penn State. Rohan serves as Industry Co-Chair for MSST, sits on the FMS Conference Advisory Board, reviews for ACM Transactions on Storage, and has served on the FAST and OSDI Artifact Evaluation Committees.

Ronnie Sahlberg is a maintainer of libiscsi, libnfs and libsmb2.

Nader has spent his career leading technology teams and driving company success for over 30 years. He led the STEC Engineering department and launched the Enterprise SSD Market. More recently Nader led a team at Western Digital in its Enterprise SSD product platform. In 2013, he co-founded NGD Systems to develop an emerging solution to the SSD market, creating the world’s first Computational Storage device. 

Mahinder Saluja, Director of SSD Technology and Pathfinding at KIOXIA America, Inc., has 20+ years of engineering leadership in innovative storage technologies development, building teams and product delivery. He has several pending storage related patents.

Jacob Schmier is a Principal Firmware Engineer at Sandisk, developing enterprise SSD firmware for next‑generation platforms. His work centers on implementation and technical leadership driving performance, reliability, and efficiency in data‑center storage.

Dr. Endric Schubert is a computer systems architect and co-founder of Missing Link Electronics where he focuses on low-latency processing architectures. His background includes software engineering, FPGA technology, Reconfigurable Computing and Embedded Systems design. Endric did his Diploma in Electrical Engineering at the University of Karlsruhe, Germany and his PhD in Computer Science at the University of Tuebingen, Germany. He has authored various technical publications and is the inventor of several patents.

Vivek is a Staff Engineer with the GOST team at Samsung Electronics, where he focuses on the co-design of widely deployed open source system software with emerging storage and memory hardware. His work centers on rethinking system architectures to better align software with the capabilities of next-generation storage and memory technologies. He holds a PhD in database systems and has experience in distributed and decentralized systems. His work focuses on experimental research with an emphasis on real-world impact, combining scientific approaches with practical system design in industrial settings.

Dingsen Shi is a Ph.D. student in Computer Science and Engineering at the University of North Texas, focusing on storage systems, AI infrastructure, and hardware/software co-design for LLM serving. His research explores how emerging AI workloads interact with the storage stack, including KV-cache management, SSD offloading, NVMe-based data movement, and system-level performance characterization. He has industry experience in storage and chip architecture, with work spanning NVMe SSD systems, computational storage, PCIe/NVMe data paths, and accelerator-oriented system design. His current research investigates how LLM KV-cache offloading behaves at the block-device layer and how future storage systems can be redesigned to better support AI inference workloads.

David Slik is a scientist and data storage researcher at the Huawei Canadian Research Institute. Before working at Huawei, he was a Technical Director at NetApp and a co-founder of Bycast, where he led the development of StorageGRID. He has 25+ years of experience in the design, development and productization of high-performance distributed storage systems, resulting in over 90 granted patents. David is an author of two ISO/IEC standards, a contributor to five other storage industry standards organizations, and a chair of the Cloud Storage Technical Work Group at SNIA and the Power Work Group at MLCommons.

Gary Smerdon is the CEO and founder of MEXT. Before MEXT, Gary served as CEO at TidalScale and held numerous leadership positions including at Fusion-io, LSI, and AMD. He is a recognized innovator having led key efforts around industry transitions in networking, storage, and computing.

Inho Song is a Ph.D. student in Computer Science at Virginia Tech. His research focuses on storage systems, with an emphasis on emerging SSD interfaces and architectures such as NVMe Flexible Data Placement (FDP) and Zoned Namespace (ZNS) SSDs. His work combines empirical characterization, systems design, and emulation to better understand device behavior and improve the interaction between storage hardware and software.

Ross Stenfort is a Distinguished Engineer at SanDisk, driving storage innovation and industry collaboration. He is an active collaborator with industry organizations including OCP, SNIA/SFF, and NVM Express. Over his career, he has developed Storage Systems, SSDs, ROCs and HBAs and achieving 40+ patents. With 30+ years of experience across Meta, CNEX, Seagate, LSI, SandForce, SiliconStor, and Adaptec, Ross brings a broad and deep perspective on the storage ecosystem. He holds a B.S. in Electronic Engineering from Cal Poly, San Luis Obispo.

Curtis Stevens (Strategist, Seagate Technology) has been working in the storage industry for over 35 years with experience in host side drivers, HBA design, Hard disk drives, SSD’s, SAS/SATA/USB/1394/etc. Curtis is the technical editor for standards and specifications in INCITS T10, INCITS T13, SATA-IO, USB-IF, NVMe, and others. Curtis has helped invent and standardize technologies in the areas of Bootable CD-ROM, PATA-SATA bridges, USB Printers, USB Mass Storage, translating SAS to SATA, 4K/512e sector sizes, NVMe Zoned Name Spaces, and most recently, Drive Regeneration/depopulation & Translating SAS to NVMe.

Himabindu Tummala is a Distinguished Engineer based in Hopkinton, Massachusetts, with deep expertise in large‑scale storage systems and distributed data architectures. Her work focuses on building AI‑ready data platforms, spanning data preparation and object‑based infrastructures that support modern analytics and AI workloads.

Wes Vaske is a Senior Member of Technical Staff at Micron Technology. As a Storage Solutions Architect with over 15 years of experience in data center storage systems, he is currently focused on developing high-performance NVMe solutions for AI workloads. 

He has been a lead contributor to the MLPerf Storage Working Group helping to define industry benchmarks for AI storage performance. 

Wes is a frequent presenter at Future of Memory and Storage (FMS) and SNIA Developer Conference (SDC) and Chairs the SNIA AI Data Workloads Technical Working Group (TWG) Prior to his current role, Wes was a Systems Performance Engineer with the Data Center Workloads Engineering team for more than a decade, where he pioneered system observation, tracing, and analysis tools as well as developing automation frameworks enabling reproducible and insightful performance analysis across diverse environments that have become foundational to Micron’s workload-first product development strategy. 

His earlier career includes performance engineering for Oracle RAC database systems at Dell Technologies. Wes holds a B.S. in Physics from Iowa State University and continues to drive innovation at the intersection of storage, AI, and systems performance.

Zhe Wang builds highly durable, scalable, and secure storage layers for the modern cloud. As a Distinguished Engineer at Broadcom, he leads the storage layer for the Scalable Cloud File System, driving its native deployments across AWS, Azure, and GCP. With over 10 years of deep storage system experience, his career is defined by tackling complex data challenges. At Broadcom (which he joined via the Datrium acquisition), he developed the Ransomware Encryption Detection engine for their Ransomware Recovery solution and heavily contributed to the VLCR file system. At Datrium, he led the foundational storage pool and encryption layers. Zhe’s impact extends beyond traditional file systems; his Ph.D. research in Computer Science produced Multi-Probe LSH, a foundational technique that continues to power today's modern vector databases.

S. Windh received a Ph.D. in computer science from the University of California (Riverside, California, USA) in 2018. He was a Research Assistant at the Embedded Systems Lab during his studies. He is currently an MTS Systems Software Engineering in the TPG Storage and Memory Systems Pathfinding group at Micron Technology, Inc. (Richardson, Texas USA). His research interests include multithreading and parallelism, reconfigurable-computing architectures and tools, and high-performance computing and applications. He co-led the Software Architecture for Micron's Memory Lake investigation with Pacific Northwest National Labs exploring disaggregated shared memory with near memory compute capabilities. He is currently leading a project exploring emulating High IOPS storage drives for AI workloads and extending Nvidia’s Dynamo to support CXL shared memory.

Daniel Worledge is a Distinguished Research Scientist and the Senior Manager of MRAM at the IBM Almaden Research Center. He leads teams in Yorktown Heights and Albany in New York, and in San Jose in California, doing scientific research and technology development of magnetoresistive random access memory (MRAM). He made the first perpendicular CoFeB|MgO tunnel junctions and led the IBM team that demonstrated the first integrated perpendicular Spin-Transfer-Torque MRAM, with ultra-low write-error-rate. Dr. Worledge invented and developed Current-in-Plane Tunneling as a fast turn-around measurement method for magnetic tunnel junctions. He received a BA in Physics and Applied Mathematics from UC Berkeley in 1995 and a PhD in Applied Physics from Stanford University in 2000, with a thesis on spin-polarized tunneling in oxide ferromagnets. Dr. Worledge received the 2025 IEEE Cledo Brunetti Award, is a Fellow of APS and IEEE, and is a member of the National Academy of Engineering.

Yadavendra Yadav is a Software Architect at IBM Systems Development Labs with over 22 years of industry experience in Linux kernel development, filesystems, device drivers, containers technologies including Docker and Kubernetes, and OpenStack Swift. Over the past decade at IBM, he has focused on kernel filesystems, RAID technologies, erasure coding, and container platforms, contributing to the design and development of scalable and high-performance storage infrastructure solutions.

Heesung Yang is a Software Engineer at Samsung Electronics, focusing on system software and storage platforms. His work spans CI infrastructure, Linux server modules, high-availability database clients, and storage system optimization. He has contributed to CI system development, Linux-based disk group management, and PostgreSQL clients for high-availability environments. He also worked on telemetry integration and failure analysis tools to enhance system observability and reliability. He played a key role in developing the Seamless FDP feature to automatically optimize write amplification factor (WAF), and is currently working on JBOF-level computation offloading.