SNIA Developer Conference (SDC)

S. Windh received a Ph.D. in computer science from the University of California (Riverside, California, USA) in 2018. He was a Research Assistant at the Embedded Systems Lab during his studies.
He is currently an MTS Systems Software Engineering in the TPG Storage and Memory Systems Pathfinding group at Micron Technology, Inc. (Richardson, Texas USA). His research interests include multithreading and parallelism, reconfigurable-computing architectures and tools, and high-performance computing and applications. 
He co-led the Software Architecture for Micron's Memory Lake investigation with Pacific Northwest National Labs exploring disaggregated shared memory with near memory compute capabilities. He is currently leading a project exploring emulating High IOPS storage drives for AI workloads and extending Nvidia’s Dynamo to support CXL shared memory.

Jacob Schmier is a Senior Technologist in Firmware Engineering at Sandisk, developing enterprise SSD firmware for next‑generation platforms. His work centers on implementation and technical leadership driving performance, reliability, and efficiency in data‑center storage.

Stephen Bates is an Fellow in the AI Business Unit at AMD, where he leads work on communication and storage architectures and associated software for AI and data-centric systems. He is a recognized expert in high-performance technologies including NVMe, RDMA, TCP/IP, and non-volatile memory, with deep experience developing complex storage and communication solutions such as NVMe controllers and PCIe switching fabrics.

Stephen thrives at the intersection of hardware and software, bridging architectural innovation with practical implementation. He is an active contributor to the Linux kernel and other open-source projects that advance system performance and scalability.

Prior to AMD, Stephen served as Assistant Professor of Computer Engineering at the University of Alberta. He holds a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Filip Blagojevic is a Research Scientist at Western Digital. His research focuses on storage systems, high-performance computing, distributed systems, and system-level optimization for data-intensive workloads. He received his PhD in Computer Science from Virginia Tech in 2008 and previously worked at Lawrence Berkeley National Laboratory.

His recent work explores storage and systems support for emerging AI workloads, including LLM inference, KV-cache management, and memory/storage tiering. He has also worked extensively on Linux file systems, HDD-SMR storage, Hadoop/HDFS, erasure coding, and performance characterization of large-scale storage systems.

Jeff Bromberger is an engineer on the Storage Core team at Microsoft. Prior to joining Microsoft in 2023, he was co-owner of Kernel Drivers and worked as a Windows driver consultant for over 20 years.

Satananda Burla is a Distinguished Engineer at Marvell, involved in the design and development of Marvell Octeon SoC architecture. He is also involved in the design and development of Networking, Memory/Storage, and Security solutions involving multiple Marvell product lines. He represents Marvell at OPI, OASIS, IBTA, UEC, and other technical forums.

Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Core Datacenter Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP, serves on the SNIA board, and co-chairs the SFF TWG and community.  Anthony has over 26 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Clarete Crasta is a Principal Engineer in Hewlett Packard Enterprise, currently working in the HPC and AI Advance Development group. She is a well-recognized technical architect and has built a solid reputation over 20 years with deep system software expertise in High Performance Computing, memory and storage technologies, operating systems kernel, platform & IO, and virtualization. Her ability to drive and lead teams, focus on customers, willingness to take up any complex work in newer areas, effective communication skills, and active collaboration has gained her acceptance across the community. Clarete has experience leading and collaborating across teams, business units,  customers and partners. She is a co-inventor on 13 US filed patents and has co-authored 7 publications. She has presented at various conferences such as SNIA CMS, SNIA SDC, CUG, GHCI on Fabric Attached Memory and related topics. She has worked as a member of the technical committee and review board for GHCI, IEEE and is serving as Industry Track Chair for IC2E. She holds a master’s degree in software engineering and bachelor’s in electrical engineering

Jason is a Distinguished Engineer at Dell Technologies, working in the Storage Chief Technology Office. His role involves leading the development of next-generation storage and network protocols for both Public and Private Clouds. Jason also serves as Chair of the SNIA Accelerated Object I/O Technical Working Group. Throughout his career, Jason has focused on enterprise storage and meeting the needs of customers who want to expand beyond the traditional on-premises data center. He enjoys collaborating with customers and partners to understand their requirements when transforming their business. In his personal life, Jason is passionate about running marathons and baking artisan bread. He lives in Newton, Massachusetts, with his wife and their three children.

Alessandro Goncalves is a Storage Solutions Architect specializing in high-performance storage systems, AI/ML infrastructure, and workload-aware performance engineering. Currently at Solidigm, he focuses on architecting and benchmarking SSD-based solutions for emerging AI and inference workloads, collaborating with organizations such as MLCommons to evaluate next-generation storage behavior for data-intensive AI pipelines.

His background includes persistent memory architecture and performance engineering work at Intel, where he contributed to solutions involving Optane and large-scale storage performance analysis across enterprise and hyperscale environments. His recent work centers on AI-oriented storage observability, workload fingerprinting, vector database benchmarking, KV-cache infrastructure, and cross-layer latency attribution for modern storage systems.

Kalyan Gunda is a Senior Distinguished Engineer and Chief Architect for Unstructured Storage at Dell Technologies, focused on scalable object storage and distributed data platforms. He brings deep expertise across S3/object storage, distributed file systems, and data protection, helping enterprises simplify data infrastructure for modern, data‑intensive workloads. Kalyan works at the intersection of storage and AI, shaping how application‑driven, API‑first storage models enable scalable data pipelines for next‑generation workloads

Abhishek Gupta is a Storage Architect at Cerebras Systems, where he designs next-generation storage infrastructure for large-scale AI training and inference workloads. He brings over 15 years of experience building distributed storage systems, file systems, and high-performance I/O stacks. Previously, he worked as Senior Staff at Huawei's Research Centre, with earlier principal and senior engineering roles at Dell EMC (Isilon OneFS, Data Domain), DDN, NetApp, and Veritas. His work spans GPU Direct Storage, File-over-Memory, CXL, computational storage, and distributed file systems.

Chih-Tsung Huang is the Senior Director of Hardware Engineering in the Common Hardware Group. Chih-Tsung is responsible for delivering Sustainable AI infrastructure solutions for silicon, hardware systems and optics in Cisco’s switching, routing, optical, access and IoT portfolios. Chih-Tsung has over 100 US and Global patents covering a breadth of topics including but not limited to sustainability, silicon, FPGA, networking, compute, security and storage.

20 years of experience working on parallel file systems

Trent Johnson is a Hardware Architect at IBM, with a focus on the IBM FlashCore Module (Solid State Drive). He joined IBM as part of the Cleversafe Acquisition where he was the System Hardware Architect of exabyte-scale Object Storage. Prior to Cleversafe, he developed system-level manufacturing and test solutions for AMD CPUs and GPUs where he was awarded the AMD Corporate Technical Achievement Award. 
He has 27 years of industry experience, holds 7 US patents and has published at the Future of Memory and Storage, SNIA Developer Conference, Burn-in and Test Socket Workshop as well as the Conference for Consumer Electronics. He earned BSEE and MSEE degrees from The University of Texas at Austin in Electrical Engineering with a focus on Manufacturing System Engineering.

Keith MacLean is a Member of Technical Staff and System Architect at Micron Technology, where he focuses on enterprise SSD architecture, power efficiency, and next-generation storage platform design.

Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives HPC strategy and the technical IO roadmap in NVIDIA GPU Cloud, focused on pushing the envelope for storage and networking programming models at scale, data center architecture and security, and scaled systems.

He is a community builder with a passion for building an ecosystem that extends the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. He co-leads the Storage-Next effort to optimize products for IOPs/TCO.

He tinkers with and leverages NVIDIA and vendor products in a lab packed with scaled compute, storage and networking gear to apply and extend new tech. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.

Rohan Puri is a Senior Staff Engineer at DataDirect Networks (DDN), working on the Infinia IO Path. Previously he was a Staff Engineer at Samsung Semiconductor working on distributed file systems. He has worked across the Linux storage stack for over 14 years, including filesystem development at Oracle, Veritas, and contributions to OpenZFS. He holds a Masters in Computer Science from Penn State. Rohan serves as Industry Co-Chair for MSST, sits on the FMS Conference Advisory Board, reviews for ACM Transactions on Storage, and has served on the FAST and OSDI Artifact Evaluation Committees.

Lisa Rivalin is a Systems Engineer on the Hardware Design team at Meta, where she has worked for six years. She applies data and AI methods to hardware engineering challenges. 

Currently, Lisa leads efforts to estimate and reduce the carbon footprint of Meta IT hardware inventory, and evaluates new server technologies to propose lower-impact designs. 

Previously at Meta, she led a digital twin initiative that combined physics-based modeling and machine learning to optimize data center design and operations.

Before Meta, Lisa was a research scientist at Engie, developing energy performance contracts and smart building technologies, and an affiliate research scientist at Lawrence Berkeley National Laboratory. She holds a PhD in Applied Statistics and Energy from Mines ParisTech, an MSc in Engineering from the University of Poitiers, and an MA in History and Philosophy of Science from Paris Diderot University.

Inho Song is a Ph.D. student in Computer Science at Virginia Tech. His research focuses on storage systems, with an emphasis on emerging SSD interfaces and architectures such as NVMe Flexible Data Placement (FDP) and Zoned Namespace (ZNS) SSDs. His work combines empirical characterization, systems design, and emulation to better understand device behavior and improve the interaction between storage hardware and software.

Himabindu Tummala is a Distinguished Engineer based in Hopkinton, Massachusetts, with deep expertise in large‑scale storage systems and distributed data architectures. Her work focuses on building AI‑ready data platforms, spanning data preparation and object‑based infrastructures that support modern analytics and AI workloads.

Wes Vaske is a Senior Member of Technical Staff at Micron Technology. As a Storage Solutions Architect with over 15 years of experience in data center storage systems, he is currently focused on developing high-performance NVMe solutions for AI workloads.

He has been a lead contributor to the MLPerf Storage Working Group helping to  define industry benchmarks for AI storage performance. Wes is a frequent presenter at Future of Memory and Storage (FMS) and SNIA Developer Conference (SDC) and Chairs the SNIA AI Data Workloads Technical Working Group (TWG)

Prior to his current role, Wes was a Systems Performance Engineer with the Data Center Workloads Engineering team for more than a decade, where he pioneered system observation, tracing, and analysis tools as well as developing automation frameworks enabling reproducible and insightful performance analysis across diverse environments that have become foundational to Micron’s workload-first product development strategy.

His earlier career includes performance engineering for Oracle RAC database systems at Dell Technologies.

Wes holds a B.S. in Physics from Iowa State University and continues to drive innovation at the intersection of storage, AI, and systems performance.

Zhe Wang builds highly durable, scalable, and secure storage layers for the modern cloud. As a Distinguished Engineer at Broadcom, he leads the storage layer for the Scalable Cloud File System, driving its native deployments across AWS, Azure, and GCP. With over 10 years of deep storage system experience, his career is defined by tackling complex data challenges. At Broadcom (which he joined via the Datrium acquisition), he developed the Ransomware Encryption Detection engine for their Ransomware Recovery solution and heavily contributed to the VLCR file system. At Datrium, he led the foundational storage pool and encryption layers. Zhe’s impact extends beyond traditional file systems; his Ph.D. research in Computer Science produced Multi-Probe LSH, a foundational technique that continues to power today's modern vector databases.